What is PRU ICSS?
Overview. The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors. The PRU-ICSS firmware runs on the PRU cores, offloading the time-critical link layer processing from the main ARM processor, running TI-RTOS.
What is a BeagleBone black?
BeagleBoard BeagleBone® Black is a low-cost, community-supported development platform for developers and hobbyists, based on the Sitara AM3358BZCZ100 Arm Cortex-A8 32-Bit RISC microprocessor from Texas Instruments.
What is a Pru microcontroller?
A programmable real-time unit (PRU) is a fast (200-MHz, 32-bit) processor with single-cycle I/O access to a number of the pins and full access to the internal memory and peripherals on the AM3358 processor on BeagleBones (BeagleBone, BeagleBone Black, BeagleBone Green, etc.).
What is BeagleBone Pru?
The BeagleBone Black is an inexpensive, credit-card sized computer that has two built-in microcontrollers called PRUs. While the PRUs provide the real-time processing capability lacking in Linux, using these processors has a learning curve.
Can a PRU remux an AM335x on the fly?
As a consequence, the pin mux logic will either connect a GPIO to a bit in a PRU’s R30 (output register) or R31 (input register), but not both at the same time. While the AM335x can be re-muxed on the fly, the PRU cannot perform this procedure in order to attain bi-directional access to a GPIO. Only the Cortex A8 can remux the chip.
Where can I find the PRU assembly instructions?
The complete list of PRU assembly instructions can be found at TI. Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 – 10) The documentation on the subsystem is here. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.
How does a PRU work on a host?
Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively. By probing these registers, a PRU can determine if an interrupt is currently present on each host channel. Both PRUs have the ability to have GPIO pins tied directly to registers for simultaneous reading or commanding of GPIOs.
What does register 31 in elinux mean for Pru?
Register 31 allows for control of the INTC for the PRU. Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively. By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.